SRAM may be the easiest volatile memory to use, but it is not the least expensive in significant densities. Each bit of memory requires between four and six transistors. When millions or billions of bits are required, the complexity of all those transistors becomes substantial. Dynamic RAM, or DRAM, takes advantage of a very simple yet fragile storage component: the capacitor. A capacitor holds an electrical charge for a limited amount of time as the charge gradually drains away. As seen from EPROM and flash devices, capacitors can be made to hold charge almost indefinitely, but the penalty for doing so is significant complexity in modifying the storage element. Volatile memory must be both quick to access and not be subject to write-cycle
limitations—both of which are restrictions of nonvolatile memory technologies.
When a capacitor is designed to have its charge quickly and easily manipulated, the downside of rapid discharge emerges. A very efficient volatile storage element can be created with a capacitor and a single transistor but that capacitor loses its contents soon after being charged. This is where the term dynamic comes from in DRAM—the memory cell is indeed dynamic under steadystate conditions. The solution to this problem of solid-state amnesia is to periodically refresh, or update, each DRAM bit before it completely loses its charge. As with SRAM, the pass transistor enables both reading and writing the state of the storage element.
However, a single capacitor takes the place of a multitransistor latch. This significant reduction
in bit complexity enables much higher densities and lower per-bit costs when memory is
implemented in DRAM rather than SRAM. This is why main memory in most computers is implemented using DRAM. The trade-off for cheaper DRAM is a degree of increased complexity in the memory control logic. The number one requirement when using DRAM is periodic refresh to maintain the contents of the memory.
DRAM is implemented as an array of bits with rows and columns as shown in Fig. 4.10. Unlike
SRAM, EPROM, and flash, DRAM functionality from an external perspective is closely tied to its
row and column organization. SRAM is accessed by presenting the complete address simultaneously. A DRAM address is presented in two parts: a row and a column address. The row and column addresses are multiplexed onto the same set of address pins to reduce package size and cost. First the row address is loaded, or strobed, into the row address latch via row address strobe , or RAS*, followed by the column address with column address strobe
, or CAS*. Read data propagates to the output after a specified access time. Write data is presented at the same time as the column address, because it is the column strobe that actually triggers the transaction, whether read or write. It is during the column address phase that WE* and OE* take effect.
limitations—both of which are restrictions of nonvolatile memory technologies.
When a capacitor is designed to have its charge quickly and easily manipulated, the downside of rapid discharge emerges. A very efficient volatile storage element can be created with a capacitor and a single transistor but that capacitor loses its contents soon after being charged. This is where the term dynamic comes from in DRAM—the memory cell is indeed dynamic under steadystate conditions. The solution to this problem of solid-state amnesia is to periodically refresh, or update, each DRAM bit before it completely loses its charge. As with SRAM, the pass transistor enables both reading and writing the state of the storage element.
However, a single capacitor takes the place of a multitransistor latch. This significant reduction
in bit complexity enables much higher densities and lower per-bit costs when memory is
implemented in DRAM rather than SRAM. This is why main memory in most computers is implemented using DRAM. The trade-off for cheaper DRAM is a degree of increased complexity in the memory control logic. The number one requirement when using DRAM is periodic refresh to maintain the contents of the memory.
DRAM is implemented as an array of bits with rows and columns as shown in Fig. 4.10. Unlike
SRAM, EPROM, and flash, DRAM functionality from an external perspective is closely tied to its
row and column organization. SRAM is accessed by presenting the complete address simultaneously. A DRAM address is presented in two parts: a row and a column address. The row and column addresses are multiplexed onto the same set of address pins to reduce package size and cost. First the row address is loaded, or strobed, into the row address latch via row address strobe , or RAS*, followed by the column address with column address strobe
, or CAS*. Read data propagates to the output after a specified access time. Write data is presented at the same time as the column address, because it is the column strobe that actually triggers the transaction, whether read or write. It is during the column address phase that WE* and OE* take effect.
