It has been shown that clock signals regulate the operation of a state-full digital system by causing new values to be loaded into flops on each active clock edge. Synchronous logic is the general term for a collection of logic gates and flops that are controlled by a common clock. The ripple counter is not synchronous, even though it is controlled by a clock, because each flop has its own clock, which leads to the undesirable ripple output characteristic previously mentioned. A synchronous circuit has all of its flops transition at the same time so that they settle at the same time, with a resultant improvement in performance. Another benefit of synchronous logic is easier circuit analysis, because all flops change at the same time.
Designing a synchronous counter requires the addition of logic to calculate the next count value
based on the current count value. Figure 1.15 shows a high-level block diagram of a synchronous
counter and is also representative of synchronous logic in general. Synchronous circuits consist of
state-full elements (flops), with combinatorial logic providing feedback to generate the next state
based on the current state. Combinatorial logic is the term used to describe logic gates that have no state on their own. Inputs flow directly through combinatorial logic to outputs and must be captured by flops to preserve their state.
An example of synchronous logic design can be made of converting the three-bit ripple counter
into a synchronous equivalent. Counters are a common logic structure, and they can be designed in a variety of ways. The Boolean equations for small counters may be directly solved using a truth table and K-map. Larger counters may be assembled in regular structures using binary adders that generate the next count value by adding 1 to the current value. A three-bit counter is easily handled with a truth-table methodology.
